An implementation method of a RSA crypto processor based on modified Montgomery algorithm

In this paper, a new implementation method to optimize a 1024-bit RSA crypto processor is presented. By analyzing and improving high-radix Montgomery algorithm and FIPS method we propose a new algorithm that is suitable for signature card application. A corresponding RAM management approach is introduced. We have improved the former architecture of two multipliers computing in parallel so that the longest critical path of the whole design is greatly shortened. Performance analysis is performed. As a case study, a 1024-bit RSA crypto processor is implemented. The average operating time to calculate 1024-bit modular exponentiation is 1.58M cycles. Based on TSMC 0.25μm standard cell library, the synthesis gate count is about 36K and the highest frequency is 66M. At this speed, 1024-bit message encryption needs only 27.7ms.