Title :
A high speed data encryption processor for public key cryptography
Abstract :
A cost-effective public key cryptographic architecture and its implementation in 2-μm double-level-metal CMOS are presented. The latter consists of a 593-bit arithmetic processing element, an 8-bit microcontroller, and an intelligent bus interface unit. The device uses 95000 transistors, has an area of 115000 mil2 assembled in a 40-pin package, and is capable of an average throughput of 500 kb/s
Keywords :
CMOS integrated circuits; VLSI; computer interfaces; cryptography; microprocessor chips; shift registers; 2 micron; 40-pin package; 500 kbit/s; 593 bit; 8 bit; 8-bit microcontroller; arithmetic processing element; cost-effective; data encryption processor; double-level-metal CMOS; high speed; implementation; intelligent bus interface unit; public key cryptographic architecture; public key cryptography; throughput;
Conference_Titel :
Custom Integrated Circuits Conference, 1989., Proceedings of the IEEE 1989
Conference_Location :
San Diego, CA, USA
DOI :
10.1109/CICC.1989.56740
