DocumentCode :
2688477
Title :
A bit-serial VLSI receptive field accumulator
Author :
Strohbehn, Kim ; Andreou, Andreas G.
fYear :
1989
fDate :
15-18 May 1989
Abstract :
A digital bit-serial VLSI chip for accumulating neural activations of a population of neurons that form a linear receptive field is discussed. This type of VLSI circuit is complementary to the best-match classifiers described in the literature. The circuit is called a brute force detector (BFD). The authors have designed and fabricated a prototype BFD neuron cascade through MOSIS in a 3-μm p-well CMOS process (M83M run). The results indicate that a wafer-scale, restructurable version of a detector could be constructed that could implement on the order of 105 receptive fields. A receiver using a cascade of such wafers would be of great practical value for radar and sonar applications as well as useful for the search for extraterrestrial intelligence (SETI)
Keywords :
CMOS integrated circuits; VLSI; digital integrated circuits; neural nets; parallel processing; 3 micron; CMOS; M83M run; MOSIS; SETI; VLSI circuit; WSI; accumulating neural activations; brute force detector; digital bit-serial VLSI chip; linear receptive field; neuron cascade; radar; receptive field accumulator; search for extraterrestrial intelligence; sonar applications; wafer scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Custom Integrated Circuits Conference, 1989., Proceedings of the IEEE 1989
Conference_Location :
San Diego, CA, USA
Type :
conf
DOI :
10.1109/CICC.1989.56742
Filename :
5726209
Link To Document :
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