Finite element analysis of reliability on compliant wafer level packaging with compliant layer

Along with electronic products developing toward lighter, thinner, and multi-functional integration, chip scale package (CSP) has been widely used in electronic packages. Wafer level packaging (WLP) has become one dominant technology. However, applications of WLP are limited by solder joint fatigue due to stress generated by the CTE mismatch among different materials. Compliant wafer level packaging (CWLP) technology can be used to enhance thermal fatigue reliability of packages greatly. Structure of CWLP with compliant layer is introduced firstly. Subsequently, ANSYS software is employed, a quarter 3D model is developed based on 128MB DDR SDRAM, and the model is loaded on four thermal cycles from -40degC to 125degC. Finally, by combining simulation results with FEM results and experimental results in other studies, comparative analyses are performed based on different thickness of compliant layer. FEM results show that, CWLP structure with compliant layer studied is reasonable in relieving the stress generated by CTE mismatch. Parameters, such as thickness of compliant layer and compliant material, are both important factors impact reliability of solder joint greatly. Thermal fatigue reliability can be significantly improved by reasonable selections of these parameters.