Title :
Architecture of a post-OPC silicon verification tool
Author :
Xiaolang Yan ; Ye Chen ; Zheng Shi
Author_Institution :
Inst. of VLSI Design, Zhejiang Univ., Hangzhou, China
Abstract :
With the wider usages of OPC and PSM technologies in current UDSM IC manufacturing, a new step of verifying the layout modifications is needed. Reasons to employ such a step are discussed in this paper. The architecture of a post-OPC silicon verification tool which has the full capability to accomplish such a verification task is presented in detail. Process modelling and some accelerating algorithms implemented in this tool are detailed as well. Real verification examples are also demonstrated.
Keywords :
integrated circuit layout; integrated circuit manufacture; integrated circuit testing; proximity effect (lithography); semiconductor process modelling; silicon; PSM technologies; Si; UDSM IC manufacturing; accelerating algorithms; optical proximity correction; phase shifting mask; post-OPC silicon verification tool; process modelling;
Conference_Titel :
ASIC, 2003. Proceedings. 5th International Conference on
Print_ISBN :
0-7803-7889-X
DOI :
10.1109/ICASIC.2003.1277471
