DocumentCode
2688547
Title
Architecture of a post-OPC silicon verification tool
Author
Xiaolang Yan ; Ye Chen ; Zheng Shi
Author_Institution
Inst. of VLSI Design, Zhejiang Univ., Hangzhou, China
Volume
2
fYear
2003
fDate
21-24 Oct. 2003
Firstpage
1365
Abstract
With the wider usages of OPC and PSM technologies in current UDSM IC manufacturing, a new step of verifying the layout modifications is needed. Reasons to employ such a step are discussed in this paper. The architecture of a post-OPC silicon verification tool which has the full capability to accomplish such a verification task is presented in detail. Process modelling and some accelerating algorithms implemented in this tool are detailed as well. Real verification examples are also demonstrated.
Keywords
integrated circuit layout; integrated circuit manufacture; integrated circuit testing; proximity effect (lithography); semiconductor process modelling; silicon; PSM technologies; Si; UDSM IC manufacturing; accelerating algorithms; optical proximity correction; phase shifting mask; post-OPC silicon verification tool; process modelling;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC, 2003. Proceedings. 5th International Conference on
ISSN
1523-553X
Print_ISBN
0-7803-7889-X
Type
conf
DOI
10.1109/ICASIC.2003.1277471
Filename
1277471
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