DocumentCode
2688558
Title
Library building for sub-micron CMOS process
Author
Kai Zhang ; Wang Dong-hui ; Li Yungang
Author_Institution
Inst. of Acoust., Chinese Acad. of Sci., Beijing, China
Volume
2
fYear
2003
fDate
21-24 Oct. 2003
Firstpage
1369
Abstract
A library, including standard cell library and IO library, was built for sub-micron CMOS process. The process of the library adopted is NEC 0.25 micrometers N well process. There are more than 190 cells in the library totally. The library can realize all kinds of logics, and it can be used for synthesis, simulation, place and route. The work temperature of the library is from -40°C to 125°C. In addition, some special cells are included in the library.
Keywords
CMOS integrated circuits; logic design; logic simulation; -40 to 125 C; 0.25E-6 m; IO library; N well process; NEC; library building; standard cell library; submicron CMOS process;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC, 2003. Proceedings. 5th International Conference on
ISSN
1523-553X
Print_ISBN
0-7803-7889-X
Type
conf
DOI
10.1109/ICASIC.2003.1277472
Filename
1277472
Link To Document