• DocumentCode
    2688565
  • Title

    Optimization of interface strength for SCSP based on uniform experimental design

  • Author

    Li, Gongke ; Yang, D.G. ; Qin, Liancheng ; Yi, Fuxi

  • Author_Institution
    Sch. of Mech. & Electr. Eng., Guilin Univ. of Electron. Technol., Guilin
  • fYear
    2008
  • fDate
    28-31 July 2008
  • Firstpage
    1
  • Lastpage
    5
  • Abstract
    There are various interfaces in the SCSP device, such as BT Substrate-adhesive, chip-adhesive, chip-EMC. Under used environment, it is intended to have delamination under hydrothermal integrated stress to result in failure. Therefore, interface delamination has become the one of major failure modes. On the one hand, in this paper, the whole distribution situations of stress under thermal loading are obtained. After carrying out these analyses, the hazard locations to the essential interface are selected showed as Fig.4. On the other hand, referring to interface delamination failure, some initial cracks are placed in stress concentration interface. The distribution of J-integral is calculated with finite element method. Finally, in order to optimize devicepsilas interface strength and enhances the device reliability, the uniform experimental design combining the finite element method is employed in this paper by choosing several structure size as factor of experimental design, such as chip, adhesive, BT Substrate and EMC. The uniform design table with 4 factors 5 levels is used to study the relationship between structure and interface strength J-integral, to optimize interface strength through changing the structure parameters. The SCSP model approximate regression function is obtained by using sample point which produces uniform experimental design and response value is calculated by Finite element method and the optimization solution with the optimization algorithm is carried out. The optimal combination to dimension is obtained under this method. The analyzing results of thermal stress show that maximum thermal stress of device appears at mount tip of the second die. The analyzing results of interface strength show that the maximum value of J-value locates at the interface between BT substrate and adhesive, the crack in this field is unstable state.
  • Keywords
    chip scale packaging; finite element analysis; SCSP; delamination; finite element method; hydrothermal integrated stress; thermal loading; uniform experimental design; Delamination; Design for experiments; Design optimization; Electromagnetic compatibility; Electronic packaging thermal management; Electronics packaging; Finite element methods; Integrated circuit packaging; Integrated circuit technology; Thermal stresses;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronic Packaging Technology & High Density Packaging, 2008. ICEPT-HDP 2008. International Conference on
  • Conference_Location
    Shanghai
  • Print_ISBN
    978-1-4244-2739-0
  • Electronic_ISBN
    978-1-4244-2740-6
  • Type

    conf

  • DOI
    10.1109/ICEPT.2008.4607125
  • Filename
    4607125