Title :
The Trap As A Control Flow Mechanism
Author :
Chandross, J.A. ; Jagadish, H.V. ; Asthana, Akshay
Author_Institution :
AT&T Bell Laboratories
fDate :
Nov. 30 1988-Dec. 2 1988
Keywords :
Hardware; Microprocessors; Monitoring; Performance evaluation; Process design; Processor scheduling; Scheduling algorithm; Testing; Vehicles; Very large scale integration;
Conference_Titel :
Microprogramming and Microarchitecture, 1988., Proceeding of the 21st Annual Workshop on
Conference_Location :
San Diego, CA, USA
Print_ISBN :
0-8186-1919-8
DOI :
10.1109/MICRO.1988.639252
