DocumentCode

2688663

Title

The Trap As A Control Flow Mechanism

Author

Chandross, J.A. ; Jagadish, H.V. ; Asthana, Akshay

Author_Institution

AT&T Bell Laboratories

fYear

1988

fDate

Nov. 30 1988-Dec. 2 1988

Firstpage

50

Lastpage

52

Keywords

Hardware; Microprocessors; Monitoring; Performance evaluation; Process design; Processor scheduling; Scheduling algorithm; Testing; Vehicles; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Microprogramming and Microarchitecture, 1988., Proceeding of the 21st Annual Workshop on

Conference_Location

San Diego, CA, USA

ISSN

0194-1895

Print_ISBN

0-8186-1919-8

Type

conf

DOI

10.1109/MICRO.1988.639252

Filename

639252