DocumentCode
2688698
Title
A monolithic 50-200 MHz CMOS clock recovery and retiming circuit
Author
Baumert, R.J. ; Metz, P.C. ; Pedersen, M.E. ; Pritchett, R.L. ; Young, J.A.
fYear
1989
fDate
15-18 May 1989
Abstract
A single-chip realization of a clock recovery and data retiming circuit is described. The circuit has been manufactured in a 0.9-μm digital CMOS technology and will recover a clock from NRZ (nonreturn-to-zero) random data. Features of the chip include built-in self-test, crystal of reference clock inputs, and differential or single-ended ECL (emitter-coupled logic) 100k I/O. A single inexpensive external crystal is required to stabilize operation over the frequency range. With the aid of a single external reference resistor, true ECL 100k compatibility is maintained without the cost and complexity of an added bipolar transistor process
Keywords
CMOS integrated circuits; automatic testing; clocks; digital integrated circuits; integrated circuit testing; timing circuits; 0.9 micron; 50 to 200 MHz; NRZ random data; built-in self-test; clock recovery; data retiming circuit; differential I/O; digital CMOS technology; emitter-coupled logic; external crystal; external reference resistor; monolithic IC; reference clock inputs; single-chip realization; single-ended ECL I/O;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 1989., Proceedings of the IEEE 1989
Conference_Location
San Diego, CA, USA
Type
conf
DOI
10.1109/CICC.1989.56754
Filename
5726221
Link To Document