Title :
High performance clock distribution for CMOS ASICs
Author :
Boon, Scot ; Butler, Scott ; Byrne, Raymond ; Setering, Brad ; Casalanda, Marty ; Scherf, Al
Abstract :
An effective clock distribution system is presented for high performance CMOS standard cell designs. The system can achieve clock skew of less than 500 ps with phase delay under 4 ns. The system is flexible, multitiered, netlist-specific, compatible with commercial routers, and accurately modeled. Clock tree structure, interconnect constraints, buffer design methodology, netlist-driven placement, localized clock assignment, simulated annealing, layout reintegration, and simulation modeling are discussed
Keywords :
CMOS integrated circuits; application specific integrated circuits; clocks; digital integrated circuits; synchronisation; 4 ns; 500 ps; CMOS ASICs; buffer design methodology; clock distribution system; clock skew; clock tree structure; digital IC; high performance CMOS; interconnect constraints; layout reintegration; localized clock assignment; netlist-driven placement; phase delay; simulated annealing; simulation modeling; standard cell designs;
Conference_Titel :
Custom Integrated Circuits Conference, 1989., Proceedings of the IEEE 1989
Conference_Location :
San Diego, CA, USA
DOI :
10.1109/CICC.1989.56761
