DocumentCode :
2688818
Title :
Rheological analysis of an underfill material
Author :
Rasiah, Ignatius J. ; Ho, P.S. ; Manoharan, M. ; Ng, C.L. ; Chau, Michael
Author_Institution :
Johnson Matthey (S) Pte. Ltd., Singapore
fYear :
1998
fDate :
8-10 Dec 1998
Firstpage :
354
Lastpage :
358
Abstract :
In microelectronics packaging, flip-chip interconnection is gaining momentum as it accommodates thinner packages, higher I/O and shorter electrical connections, hence reducing heat generation and increasing clock speed. The former should improve package reliability. Overall, it reduces manufacturing time/cost by eliminating wire bonding. It is necessary to use underfill material to improve flip-chip reliability by reducing stress on the solder bumps and the device due to thermal mismatch between substrate, solder bumps and silicon die. The low dielectric constant of the underfill also reduces noise capacitance, and minimizes crosstalk in high frequency devices. These experiments are focused on the effect of the filler level on the underfill material properties. The rheological properties of underfill determines the material´s ability to fill narrow gaps and to spread uniformly. The nature of the resin matrix, the filler shape, size and volume fraction and the flow process temperature affect the rheology. The underfill viscosity has been investigated as a function of time. It was found that viscosity increases with increasing underfill thaw time and with increasing filler percentage. The relationship between underfill flow rates and filler percentage was examined at various temperatures. From the results, the underfill flow rate was found to increase with temperature and decrease with increasing filler level. The underfill dielectric constant for different chemistries and filler types is discussed. A model for the rheological properties of the material and its relationship to the filler level is also discussed
Keywords :
capacitance; encapsulation; filled polymers; flip-chip devices; integrated circuit interconnections; integrated circuit noise; integrated circuit packaging; integrated circuit reliability; internal stresses; microassembling; permittivity; rheology; soldering; thermal stresses; viscosity; clock speed; crosstalk; device stress; dielectric constant; electrical connections; filler level; filler percentage; filler shape; filler size; filler type; filler volume fraction; flip-chip interconnection; flip-chip reliability; flow process temperature; heat generation; high frequency devices; manufacturing cost; manufacturing time; material viscosity; microelectronics packaging; narrow gap filling; noise capacitance; package I/O count; package reliability; package thickness; resin matrix; rheological analysis; rheological properties; rheological properties model; rheology; silicon die; solder bump stress; solder bumps; spread uniformity; thermal mismatch; underfill dielectric constant; underfill flow rate; underfill material; underfill material properties; underfill thaw time; underfill viscosity; wire bonding; Clocks; Crosstalk; Dielectric constant; Dielectric materials; Microelectronics; Packaging; Rheology; Temperature; Thermal stresses; Viscosity;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronics Packaging Technology Conference, 1998. Proceedings of 2nd
Print_ISBN :
0-7803-5141-X
Type :
conf
DOI :
10.1109/EPTC.1998.756029
Filename :
756029
Link To Document :
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