Title :
A 1.4 ns/64 kb RAM with 85 ps/3680 logic gate array
Author :
Kimoto, Masayoshi ; Shimizu, Hiroshi ; Ito, Yoshito ; Kohno, Kazuyuki ; Ikeda, Motohisa ; Deguchi, Tatsuya ; Fukuda, Nobutaka ; Ueda, Koichiro ; Harada, Shigeki ; Kubota, Katsuhisa
Abstract :
The authors have developed an ECL (emitter-coupled logic) 64-kb RAM with 3680-gate logic gate array LSI using bipolar technology. The address access time is 1.4 ns (typical), clock access time is 1.8 ns (typical), and the propagation delay of the logic rate is 85 ps. The chip is 13.5 mm2 in area and packaged in a 462-pin grid array
Keywords :
bipolar integrated circuits; emitter-coupled logic; integrated memory circuits; large scale integration; logic arrays; random-access storage; 1.4 ns; 1.8 ns; 462-pin grid array; 64 kbit; 85 ps; ECL; LSI; RAM; address access time; bipolar technology; clock access time; emitter-coupled logic; logic gate array; propagation delay;
Conference_Titel :
Custom Integrated Circuits Conference, 1989., Proceedings of the IEEE 1989
Conference_Location :
San Diego, CA, USA
DOI :
10.1109/CICC.1989.56765
