A throughput-on-demand address-event transmitter for neuromorphic chips

The author presents a scalable 2D address-event transmitter interface designed to take advantage of the high integration densities available with advanced submicron technology. To sustain throughput, it exploits the linear increase in the number of active neurons per row with array size, instead of counting on a linear increase in the unit-current/unit-capacitance ratio, as existing designs do. The author synthesizes an asynchronous implementation starting from a high-level specification, and presents test results from a 104×96-neuron chip fabricated in a 1.2 μm CMOS process. Reading out the state of all neurons in a selected row in parallel, and sending their spikes in a tight burst of events, yields cycle times between 40 to 70 ns-six to ten times shorter than the 420 ns minimum cycle time reported in earlier work