DocumentCode
2689009
Title
Interconnect-dominated VLSI design
Author
Ghosh, P. ; Mangaser, R. ; Mark, C. ; Rose, K.
Author_Institution
Center for Adv. Interconnect Sci. & Technol., Rensselaer Polytech. Inst., Troy, NY, USA
fYear
1999
fDate
21-24 Mar 1999
Firstpage
114
Lastpage
122
Abstract
This paper demonstrates the problems long, lossy wires pose for VLSI design as devices shrink to deep submicron dimensions. The degree to which both repeater insertion and reverse scaling of wire sizes are required to meet GHz clock frequency projections are estimated using a detailed wire distribution and a detailed processor model (RIPE). We also show how to achieve good floorplans with repeater insertion
Keywords
VLSI; digital integrated circuits; integrated circuit interconnections; integrated circuit layout; integrated circuit modelling; GHz clock frequency projections; RIPE; deep submicron dimensions; detailed processor model; digital ICs; floorplans; interconnect-dominated VLSI design; long lossy wires; repeater insertion; reverse scaling; wire distribution model; wire size; CMOS technology; Clocks; Delay effects; Frequency; Frequency estimation; Integrated circuit interconnections; MOSFETs; Performance loss; Repeaters; Very large scale integration; Wire; Wires;
fLanguage
English
Publisher
ieee
Conference_Titel
Advanced Research in VLSI, 1999. Proceedings. 20th Anniversary Conference on
Conference_Location
Atlanta, GA
ISSN
1522-869X
Print_ISBN
0-7695-0056-0
Type
conf
DOI
10.1109/ARVLSI.1999.756042
Filename
756042
Link To Document