Noise margin constraints for interconnectivity in deep submicron low power and mixed-signal VLSI circuits

The continually growth in density and complexity of integrated circuits gives a difficult challenge in wireability of deep submicron VLSI circuits, particularly the advanced low power and mixed-signal ICs, where the interconnections have been seriously limited by the noise coupling problem. In this paper, we analyse the interconnectivity of advanced deep submicron low power and mixed-signal VLSI circuits under noise margin constraints. We show that noise margin constraint for signal coupling will restrict interconnect density as well as process technology options. The maximum interconnectivity, process technology options, and physical delay etc. are analysed against the noise margin constraints, for both with and without shielding wire cases. The optimal geometry and wirings for both local and global interconnects are studied with respect to noise margin, physical delay, and interconnect cross section area etc. Constraint for maximum available interconnectivity is demonstrated for interconnect wire geometry characteristics of advanced deep submicron CMOS processes. Our study reveals that, in advanced deep submicron VLSI circuit designs, interconnects should be separated functionally. Different geometries and wiring types and perhaps different fabrication flows and processes should be utilized in one chip. Some of the interconnect layers will be thus heavily dedicated such as some for local interconnects, some for intramodule interconnects, some for global wiring, and some for ground and power etc., all with optimal geometries