DocumentCode
2689111
Title
A submicron CMOS triple level metal technology for ASIC applications
Author
Fisher, Duncan ; Chang, K.Y. ; Pintchovski, Fabio ; Klein, Jeff ; Fu, Kuan-Yu ; Lai, Steve ; Dillard, Rick
fYear
1989
fDate
15-18 May 1989
Abstract
A submicrometer CMOS triple-level metal technology has been demonstrated. The process features include: self-aligned twin-well, improved LOCOS (local oxidation of silicon)-like isolation, scaled gate-oxide thickness, and enhanced channel implants. In addition, an advanced straight wall plug technology has been used which allows the stacking of contact, via 1, and via 2 in the layout. Inverter gate delays of 103 ps have been measured on a development 16 K-gate array with 0.8-μm gate lengths
Keywords
CMOS integrated circuits; application specific integrated circuits; integrated circuit technology; metallisation; 0.8 micron; 103 ps; ASIC applications; LOCOS; Si; contact/via stacking; enhanced channel implants; gate lengths; invertor gate delays; isolation; local oxidation; monolithic IC fabrication; scaled gate-oxide thickness; self-aligned twin-well; straight wall plug technology; submicron CMOS; triple level metal technology;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 1989., Proceedings of the IEEE 1989
Conference_Location
San Diego, CA, USA
Type
conf
DOI
10.1109/CICC.1989.56781
Filename
5726248
Link To Document