A BiCMOS technology with 660 MHz vertical PNP transistors for analog/digital ASICs

Author

Soejima, K. ; Shida, A. ; Hirata, M. ; Koga, H. ; Ukai, J. ; Sata, H.

fYear

1989

fDate

15-18 May 1989

Abstract

A BiCMOS technology with a triple-diffused vertical p-n-p transistor has been developed to meet wide-bandwidth requirements for mixed analog/digital application-specific integrated circuits (ASICs). An f_T of 660 MHz and BV_ceo of over 15 V were obtained for the p-n-p transistor, by adding only one extra mask to a conventional 2.0-μm BiCMOS process (a total of 20 masks for double-layer metallization). A unity-gain frequency of 52 MHz and DC gain of over 85 dB were obtained for a single-supply operational amplifier with p-n-p first stage. A propagation delay time of 1.27 ns for a CMOS 2 NAND gate has been obtained under a 3 F/O and 3-mm-length wiring load condition

Keywords

BIMOS integrated circuits; application specific integrated circuits; digital integrated circuits; integrated circuit technology; linear integrated circuits; 1.27 ns; 15 V; 2 micron; 660 MHz; 85 dB; BiCMOS technology; NAND gate; analog/digital ASICs; application-specific integrated circuits; double-layer metallization; monolithic IC; propagation delay time; single-supply operational amplifier; triple diffused transistors; vertical PNP transistors; wide-bandwidth requirements;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1989., Proceedings of the IEEE 1989

Conference_Location

San Diego, CA, USA

Type

conf

DOI

10.1109/CICC.1989.56785

Filename

5726252