Title :
A dual-poly (n+/p+) gate, Ti-salicide, double-metal technology for submicron CMOS ASIC and logic applications
Author :
Sun, S.W. ; Swenson, M. ; Yeargain, J.R. ; Lee, C.-O. ; Swift, C. ; Pfiester, J.R. ; Bibeau, W. ; Atwell, W.
Abstract :
The process architecture and device characteristics of a submicrometer CMOS n+/p+ poly gate, Ti-salicide, double-metal technology are described. Tradeoffs among circuit shrinkability, device gain, and hot-carrier-injection susceptibility are discussed. This technology has been successfully implemented in a 0.8-μm unified-design-rule high-performance high-end MPU product
Keywords :
CMOS integrated circuits; application specific integrated circuits; integrated circuit technology; integrated logic circuits; metallisation; titanium; 0.8 micron; IC fabrication; Ti salicide gate; TiSi2-Si; circuit shrinkability; device characteristics; device gain; double-metal technology; dual poly gate; hot-carrier-injection susceptibility; logic applications; n+/p+ poly gate; process architecture; submicron CMOS ASIC; unified-design-rule;
Conference_Titel :
Custom Integrated Circuits Conference, 1989., Proceedings of the IEEE 1989
Conference_Location :
San Diego, CA, USA
DOI :
10.1109/CICC.1989.56786
