• DocumentCode
    2689251
  • Title

    A fully integrated design methodology for 100 K-gate CMOS custom LSIs with TAB packaging

  • Author

    Yamamura, Takeshi ; Kuwano, Kazusumi ; Sugatani, Shinji ; Tsujimura, Takehisa

  • fYear
    1989
  • fDate
    15-18 May 1989
  • Abstract
    A fully integrated design methodology based on a 1.0-μm CMOS standard cell technology with tape automated bonding (TAB) packaging has been developed to design and fabricate maximum 100 K-gate custom LSIs. The methodology has been successfully applied to the design of an I/O control processor. The processor was fabricated and housed in a 321-pin PGA (pin-grid-array)-type TAB package
  • Keywords
    CMOS integrated circuits; VLSI; application specific integrated circuits; packaging; 1 micron; CMOS standard cell technology; I/O control processor; TAB packaging; custom LSIs; integrated design methodology; monolithic IC; pin-grid-array; tape automated bonding;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Custom Integrated Circuits Conference, 1989., Proceedings of the IEEE 1989
  • Conference_Location
    San Diego, CA, USA
  • Type

    conf

  • DOI
    10.1109/CICC.1989.56791
  • Filename
    5726258
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2689251