DocumentCode
2689385
Title
Switched-capacitor simulation models for full-chip verification
Author
Chanak, Tom ; Chadha, Rakesh ; Singhal, Kishore
fYear
1989
fDate
15-18 May 1989
Abstract
A description is given of models and techniques used in a switched-capacitor functional model generator. The proposed method is useful for achieving functional verification of chips consisting of clock generating circuitry, switched-capacitor circuits, and other analog or digital blocks. A program, MODGENSC, has been developed which generates the model directly from the circuit description in SWITCAP. With this capability, full-chip mixed digital/analog simulation is achievable and also the simulation time is reduced significantly
Keywords
VLSI; circuit analysis computing; integrated circuit technology; switched capacitor networks; MODGENSC; SC circuits; SWITCAP; VLSI; circuit description; clock generating circuitry; full-chip verification; functional model generator; mixed digital/analog simulation; monolithic IC; simulation models; switched-capacitor circuits;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 1989., Proceedings of the IEEE 1989
Conference_Location
San Diego, CA, USA
Type
conf
DOI
10.1109/CICC.1989.56800
Filename
5726267
Link To Document