Title :
Physical design of testable VLSI: techniques and experiments
Author :
Levitt, Marc E. ; Abraham, Jacob A.
Abstract :
Static CMOS circuits can fail in ways that make the traditional stuck-at fault model and test-generation techniques inadequate. It is shown that the layout of these circuits can affect testability and in some cases reduce the number of possible faults in a design. A method is presented to analyze circuits at the symbolic layout level and to enhance testability using local transformations. A set of standard cells was designed using the layout level techniques. These standard cells are used in the MIS synthesis system to design over 100 example circuits. It is shown that the modified designs enable stuck-at tests to achieve significantly higher stuck-open fault coverage with an overhead that can be easily estimated. A synthesis strategy is presented to design easily testable random logic circuits
Keywords :
CMOS integrated circuits; VLSI; circuit analysis computing; circuit layout CAD; integrated circuit testing; integrated logic circuits; logic CAD; logic testing; CAD; MIS synthesis system; layout level techniques; local transformations; standard cells; static CMOS circuits; stuck-at tests; stuck-open fault coverage; symbolic layout level; synthesis strategy; testability; testable VLSI; testable random logic circuits;
Conference_Titel :
Custom Integrated Circuits Conference, 1989., Proceedings of the IEEE 1989
Conference_Location :
San Diego, CA, USA
DOI :
10.1109/CICC.1989.56812
