A datapath multiplier with automatic insertion of pipeline stages

The architecture of an N-×M-bit, pipelined, datapath multiplier compiler. The architecture allows the total delay through the multiplier to be broken into the individual delays through each column of the array. The algorithm that determines where pipeline stage columns should be inserted is efficient because it uses a simple model for the column delays. Since pipeline stages are inserted only where necessary, the compiler can produce an optimized multiplier that can be easily integrated into a fully pipelined system. Set-up and output delay times can also be used by the compiler to allow the designer to integrate the multiplier into a fully pipelined datapath