DocumentCode
2689787
Title
A 30 ns (600 MOPS) image processor with a reconfigurable pipeline architecture
Author
Aono, Kunitoshi ; Toyokura, Masaki ; Araki, Toshiyuki
fYear
1989
fDate
15-18 May 1989
Abstract
A 30-ns (600-MOPS) image processor is described. The 200 K-transistor chip has been fabricated in a 1.2-μm CMOS. A reconfigurable pipeline architecture with an array of nine multiplier/accumulators (MAC) is implemented by interchanging its pipelined data paths. This allows it to perform both matrix products and convolutions, systolically, for the discrete cosine transform (DCT) and transversal filters at HDTV rate. 512 by 512-pixel image data can be computed in less than 7.9 ms with sufficient resolution
Keywords
CMOS integrated circuits; VLSI; computerised picture processing; digital signal processing chips; parallel architectures; pipeline processing; 1.2 micron; 262144 pixel; 30 ns; 512 pixel; CMOS; DCT; DSP; HDTV rate; VLSI; convolutions; discrete cosine transform; image processor; matrix products; multiplier/accumulators; parallel processing; reconfigurable pipeline architecture; transversal filters;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 1989., Proceedings of the IEEE 1989
Conference_Location
San Diego, CA, USA
Type
conf
DOI
10.1109/CICC.1989.56825
Filename
5726292
Link To Document