DocumentCode
2690001
Title
Metastability of CMOS latch/flip-flop
Author
Kim, Lee-Sup ; Cline, Ron ; Dutton, Robert
fYear
1989
fDate
15-18 May 1989
Abstract
The authors present several design issues for CMOS latch/flip-flops designed for metastable-hardness, regarding optimal device size, aspect ratio, and configurations. They use AC small-signal analysis in the frequency domain rather than the time domain. This design approach is verified experimentally. The power-supply disturbance and temperature variation effects on the metastability are measured and the measurement data confirm that a reduced power supply voltage and a higher temperature cause a lower metastable resolving capability
Keywords
CMOS integrated circuits; flip-flops; frequency-domain analysis; integrated logic circuits; logic design; AC small-signal analysis; CMOS latch/flip-flop; aspect ratio; frequency domain; logic design; metastability; metastable-hardness; optimal device size; power-supply disturbance; temperature variation effects;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 1989., Proceedings of the IEEE 1989
Conference_Location
San Diego, CA, USA
Type
conf
DOI
10.1109/CICC.1989.56837
Filename
5726304
Link To Document