Title :
A 15 ns 32×32-bit CMOS multiplier with an improved parallel structure
Author :
Nagamatsu, Masato ; Tanaka, Shigeru ; Mori, Junji ; Noguchi, Tatsuo ; Hatanaka, Kazuhisa
Abstract :
A 32-bit×32-bit parallel multiplier with an improved parallel structure has been fabricated by 0.8-μm CMOS triple-level-metal interconnection technology. A unit adder that can sum four partial products concurrently has been developed. It enhances the parallelism of multiplier. The chip contains 27704 transistors with 2.68×2.71-mm2 die area. The multiplication time is 15 ns at 5-V power supply. The power dissipation is 277 mW at 10-MHz operation
Keywords :
CMOS integrated circuits; digital arithmetic; digital integrated circuits; multiplying circuits; parallel architectures; 0.8 micron; 10 MHz; 15 ns; 2.68 to 2.71 mm; 277 mW; 32 bit; 5 V; CMOS multiplier; die area; multiplication time; parallel multiplier; parallel structure; power dissipation; sum four partial products concurrently; triple-level-metal interconnection technology; unit adder;
Conference_Titel :
Custom Integrated Circuits Conference, 1989., Proceedings of the IEEE 1989
Conference_Location :
San Diego, CA, USA
DOI :
10.1109/CICC.1989.56842
