DocumentCode
2690120
Title
The architecture comparison and the VLSI implementation of the 32 bit embedded RISC
Author
Xu Ke ; Li Qiang ; Min Hao
Author_Institution
ASIC, Fudan Univ., Shanghai, China
Volume
1
fYear
2003
fDate
21-24 Oct. 2003
Firstpage
452
Abstract
In order to achieve our design goal as a low-cost and high-performance microprocessor, we compared several aspects of the popular embedded RISC architecture, such as general-purpose register file and stack-based, three-stages pipeline and five-stages one, Von Neumman architecture and Harvard counterpart, etc. By these comparisons, we adopted the most suitable architecture sets: a Harvard five-stages pipeline with a set of general-purpose register file. We also verified our design on the Aptix System Explorer MP3CF hardware verification platform and implemented on CSMC 0.6 μm CMOS process.
Keywords
VLSI; integrated circuit design; microprocessor chips; reduced instruction set computing; 32 bit embedded RISC; Aptix system explorer MP3CF hardware verification platform; CSMC 0.6 μm CMOS process; Harvard five stages pipeline architecture; VLSI implementation; Von Neumman architecture; architecture comparison; general purpose register file; microprocessor; reduced instruction set computing;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC, 2003. Proceedings. 5th International Conference on
ISSN
1523-553X
Print_ISBN
0-7803-7889-X
Type
conf
DOI
10.1109/ICASIC.2003.1277583
Filename
1277583
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