Analysis of novel low-power quasi-dynamic ratioless readout scanning shift register for CMOS imagers

The shift register based on the flip-flop has many disadvantages, such as big chip area and large power. Only simple circuit structure the dynamic shift register has two disadvantages of the leakage current and the charge sharing. In this paper a novel low-power quasi-dynamic shift register used as the readout scan circuit of the CMOS imagers, which is low power dissipation for the static power is near to 0 and only dynamic power is existed. The circuit is simple and ratioless. This circuit can reduce the area, does not exist the problem of charge sharing and can renew the lost charge through the supply power. Based on the 0.25 μm CMOS process, the low-power quasi-dynamic shift register has been simulated and tested using the software Tanner. The Average power consumed is 1.743699e-006 watts.