Zero-cost MTP high density NVM modules in a CMOS process flow

Author

Atrash, A. ; Cassuto, G. ; Chen, W. ; Dayan, V. ; Galzur, O. ; Gutman, M. ; Heiman, A. ; Hunsinger, G. ; Nahmad, D. ; Parag, A. ; Pikhay, E. ; Roizin, Y. ; Smith, B. ; Strum, A. ; Tishbi, T. ; Teggatz, R.

Author_Institution

Triune Syst., Richardson, TX, USA

fYear

2010

fDate

16-19 May 2010

Firstpage

1

Lastpage

4

Abstract

A zero-cost embedded high density MTP NVM with extensive statistical verification is presented. The family of compact single Poly modules ranging from 64 bit to 64 kbit is based on the Y-Flash concept, employing original array architectures and implemented in standard and power management (PM) 0.18 μm CMOS process flows. No special HV devices or additional masks are employed. Excellent reliability performance allowing more than 10 k program/erase cycles and 10 year data retention at 150°C is demonstrated.

Keywords

CMOS memory circuits; flash memories; random-access storage; CMOS process flow; Y-flash memory; array architectures; compact single polymodules; extensive statistical verification; masks; power management; size 0.18 mum; storage capacity 64 bit to 64 Kbit; temperature 150 degC; zero-cost MTP high density NVM modules; CMOS logic circuits; CMOS process; CMOS technology; Costs; Energy management; Logic devices; MOSFETs; Mass production; Nonvolatile memory; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Memory Workshop (IMW), 2010 IEEE International

Conference_Location

Seoul

Print_ISBN

978-1-4244-6719-8

Electronic_ISBN

978-1-4244-7668-8

Type

conf

DOI

10.1109/IMW.2010.5488313

Filename

5488313