Optimum design of snubber circuits for thyristor assemblies using an improved PSPICE thyristor model and computational intelligence

Solid-state switches for pulsed power applications require high current and voltage ratings. Advanced thyristors capable of withstanding 5 kV, 15 MA/sup 2/, and di/dt=20 kA//spl mu/s represent the state-of-the-art for the most demanding of these applications, such as electromagnetic guns. For many applications thyristors must be assembled in series and parallel configurations to increase the switch voltage and current ratings. Small differences in the reverse recovery characteristics of individual thyristors create unequal and potentially damaging voltage spikes at turn-off. The present design practice requires careful matching of device recovery characteristics and large snubber circuits for protection. An improved PSpice thyristor model is proposed that models the switching characteristics of thyristors with good accuracy. Reverse recovery and turn-off times, reverse and off-state voltages, and on-state voltage drop are modeled. Simulation results are compared to measured data from SPT402B thyristors. A 2-in-parallel by 3-in-series assembly of thyristors is repeatedly simulated in PSpice. Thyristor model parameters affecting recovery time and turn-off "snappiness" and snubber values are varied for each simulation. Voltages at turn-off for each thyristor are recorded. A neural network model of the entire simulation space is constructed to establish relationships between the model and snubber parameters and thyristor voltages. The neural network model is integrated with Evolutionary Computation algorithms to minimize the snubber size, while constraining the voltage and thyristor model parameters. A sensitivity analysis is also done.