Ni-based self-aligned silicidation (SAS) process on source and drain for planar polysilicon TFT low-voltage flash memory cell

High-density nonvolatile memory applications can benefit tremendously from three-dimensional (3D) integration wi th low power consumption. Among several proposals, the salicided source and drain planar polysilicon thin-film transistor (TFT) with metal nanocrystals (NCs) and high-k gate-stack is one of the promising candidates. The self-aligned silicidation (SAS) process is often used to reduce the source, drain and gate resistances of submicron logic MOSFET. Especially, NiSi has been proposed as a suitable silicide for SAS process due to its low resistivity, low formation temperature, and the extended thermal stability range. Furthermore, since Ni consumes the least amount of polysilicon to form a given thickness of silicide (NiSi), it has the advantage of ultrathin polysilicon layers on insulator substrates. Metal NCs were also introduced to allow thin tunnel dielectric, lower the program/erase (P/E) voltage and enhance the cycle endurance. Moreover, reduced low contact resistance by Ni-based SAS process leads to improved device characteristics and reliable process integration.