• DocumentCode
    2692132
  • Title

    The challenges and limitations on triple level cell geometry and process beyond 20 nm NAND Flash technology

  • Author

    Lee, Yunbong ; Park, Byoungjun ; Yun, DaeHwan ; Jeong, YeonJoo ; Kim, Pyoung Hwa ; Park, Ji Yul ; Yang, Hae Chang ; Cho, Myoung Kwan ; Ahn, Kun-Ok ; Koh, Yohwan

  • Author_Institution
    Flash Memory Div., Hynix Semicond. Inc., Cheongju, South Korea
  • fYear
    2010
  • fDate
    16-19 May 2010
  • Firstpage
    1
  • Lastpage
    2
  • Abstract
    This paper investigates the challenges and difficulties of TLC cell geometry and process beyond 20nm NAND technology from the viewpoint of programmed Vth level, new HCI disturbance and charge loss in the highest programmed level.
  • Keywords
    NAND circuits; flash memories; hot carriers; HCI disturbance; NAND flash technology; TLC cell geometry; charge loss; highest programmed level; size 20 nm; triple level cell geometry; Boosting; Electron traps; Electronic mail; Flash memory; Geometry; Hot carrier injection; Human computer interaction; Leakage current; Substrate hot electron injection; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Memory Workshop (IMW), 2010 IEEE International
  • Conference_Location
    Seoul
  • Print_ISBN
    978-1-4244-6719-8
  • Electronic_ISBN
    978-1-4244-7668-8
  • Type

    conf

  • DOI
    10.1109/IMW.2010.5488388
  • Filename
    5488388
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2692132