Scalability enhancement of FG NAND by FG shape modification

Author

Ganguly, Udayan ; Yokota, Yoshitaka ; Tang, Jing ; Sun, Shiyu ; Rogers, Matt ; Jin, Miao ; Thadani, Kiran ; Hamana, Hiroshi ; Leung, Garlen ; Chandrasekaran, Balaji ; Thirupapuliyur, Sunderraj ; Olsen, Chris ; Nguyen, Vicky ; Srinivasan, Swami

Author_Institution

Silicon Syst. Group, Appl. Mater. Inc., Sunnyvale, CA, USA

fYear

2010

fDate

16-19 May 2010

Firstpage

1

Lastpage

4

Abstract

Floating Gate (FG) NAND scaling has been severely challenged by the reduction of gate coupling ratio (CR) and increase in FG interference (FGI) below 30nm node. Firstly, scalability of inverted "T" shaped FG is evaluated by 3D electrostatics simulation. It is shown that coupling ratio (CR) and Floating Gate Interference (FGI) performance can be maintained at the level of 34nm technology down to 13nm node by engineering key aspects of the FG shape namely FG top width (FGW) and effective field height (EFH) in addition to conventional scaling approaches of IPD thinning and spacer k reduction. Secondly, FG shaping is demonstrated down to FGW of 3nm and EFH of 5nm using a sacrificial oxidation technology with no bird\´s beak to demonstrate fabrication feasibility.

Keywords

NAND circuits; electrostatics; 3D electrostatics simulation; FG NAND scaling; FG shape modification; FG top width; IPD thinning; effective field height; floating gate interference; gate coupling ratio; oxidation technology; scalability enhancement; size 13 nm; size 34 nm; spacer k reduction; Capacitance; Character generation; Chromium; Electrostatics; High K dielectric materials; High-K gate dielectrics; Interference; Scalability; Shape; Space technology;

fLanguage

English

Publisher

ieee

Conference_Titel

Memory Workshop (IMW), 2010 IEEE International

Conference_Location

Seoul

Print_ISBN

978-1-4244-6719-8

Electronic_ISBN

978-1-4244-7668-8

Type

conf

DOI

10.1109/IMW.2010.5488389

Filename

5488389