Title :
Steep subthreshold slope nanowire FETs with gate-induced Schottky-barrier tunneling
Author :
Li, Qiliang ; Zhu, Xiaoxiao ; Ioannou, Dimitris ; Suehle, John ; Richter, Curt
Abstract :
We report Schottky-barrier (S-B) nanowire field effect transistors (NW FETs) with high-performance characteristics brought about by gate-induced Schottky-barrier tunneling. The devices exhibit sharp subthreshold slopes (as small as 45 mV/dec), well-saturated inversion-mode IDS-VDS characteristics, and large on/off current ratios. The excellent device properties are attributed to: (i) the enhancement of tunneling through the NW FET S-B by the gate-channel-source coupling which results in sharp subthreshold slope, (ii) the clean, CMOS-compatible fabrication of NW FET leading to a high-quality dielectric/nanowire interface, and (iii) the good quality S/D barriers and low S/D series resistance associated with them. Previous studies have demonstrated high-performance nanowire and nanotube FETs with on/off current ratios ¿105 and subthreshold swings (SS´s) ¿ 100 mV/dec. The sharpness of the SS is a critical parameter in determining how small a fraction of the applied gate voltage is used to switch the device on and thus the maximum dissipated power. Previous pioneering results have shown that nanotube and nanowire FETs with SS < 60 mV/dec can be achieved based on avalanche breakdown or interband tunneling in the un-gated channel regions between the gate and S/D. Typically such devices require large drain voltages and may have large series resistance, non-saturating IDS-VDS, small on/off ratios and ambipolar conduction. The S-B NW FETs fabricated in this work exhibit sharp SS´s at low operation voltage, large on/off current ratios and inversion-mode saturating IDS-VDS.
Keywords :
Schottky barriers; avalanche breakdown; field effect transistors; nanowires; semiconductor device breakdown; tunnelling; ambipolar conduction; avalanche breakdown; field effect transistor; gate-channel-source coupling; gate-induced Schottky-barrier tunneling; high quality dielectric-nanowire interface; high-performance characteristics; steep subthreshold slope nanowire FET; ungated channel region; well-saturated inversion-mode IDS-VDS characteristics; Delay; FETs; Fabrication; Intrusion detection; Low voltage; MOSFETs; NIST; Nanoscale devices; Switches; Tunneling;
Conference_Titel :
Device Research Conference, 2009. DRC 2009
Conference_Location :
University Park, PA
Print_ISBN :
978-1-4244-3528-9
Electronic_ISBN :
978-1-4244-3527-2
DOI :
10.1109/DRC.2009.5354865