Effects of Fin Width on Device Performance and Reliability of Double-Gate n-Type FinFETs

This paper investigates the impact of fin width ( W_fins = 15, 20, and 25 nm) in a double-gate n-type FinFET on the performance and reliability of the device. Carrier conduction in the Si-fin body of FinFETs with various W_fins is also studied. The experimental results show that the threshold voltage and drain current of n-type FinFETs increases and decreases, respectively, as W_fin is reduced. A thinner W_fin FinFET exhibits greater immunity to short channel effects. In addition, according to the analysis results of low-frequency noise, the thinnest W_fin FinFET possesses the largest bulk oxide trap density (N_BOT) than that of a thicker W_fin FinFET. Moreover, the noise of the thinnest W_fin (15 nm) FinFET is largely dominated by the fluctuation of carrier number. In the hot-carrier injection (HCI) reliability test, the thinnest W_fin FinFET shows less performance degradation than those of the thicker ones. However, by removing the effect of the parasitic source/drain resistance, we believe that the volume inversion charged carriers flow through the entire thin Si-fin having a lower surface roughness and Coulomb scattering than those of thicker ones, which results in a higher carrier temperature and worsening of the reliability of the HCI.