Amorphous silicon floating-gate thin film transistor

Amorphous silicon (a-Si) based memory devices have the potential to greatly expand the functionality of a-Si thin-film transistor (TFT) circuitry. Recently, an a-Si floating gate TFT (FGTFT) based memory element has been demonstrated, but th e memory window was on ly 0.5V an d the retention time was only ~1ho ur. Furthermore, a-Si FGTFTs in general have a threshold voltage which depends on th e drain voltage. In this work, we explore the effects of tunnel dielectric deposition condition and floating gate (FG) geometry on the performance of a-Si FGTFT. Through this analysis, we achieved a-Si FGTFTs with memory windows of >4V, room temperature retention times of >150hours and threshold voltages (V¿) which are independent of the drain voltage.