PORTLESS low power mux architecture with line hard duplication

Embedded cache memories consumes a large percentage of the dynamic and static energy in System-On-Chip (SoC). Energy consumption expects to increase in advanced technologies. Write and read operations operate charging and discharging of large bitline capacitances. Multiplexors are introduced in 6 T-SRAM to reduce column size. Unfortunately read current is not reduced and even increases. Considering the 5 T Portless SRAM, an original multiplexor structure is presented that offers a significant gain in active energy consumption. The multiplexor benefits from a hard line duplication technique that copies an addressed line into an other line in one clock cycle. The advantages of the latter duplication technique are presented in details. Moreover Portless bit cell is more stable, suffers less leakage than 6 T SRAM bitcell. The paper confirms that Portless SRAM is a candidate alternative structure to 6 T SRAM in advanced technologies.