• DocumentCode
    2692475
  • Title

    Charge loss in TANOS devices caused by Vt sensing measurements during retention

  • Author

    Park, H. ; Bersuker, G. ; Gilmer, D. ; Lim, K.Y. ; Jo, M. ; Hwang, H. ; Padovani, A. ; Larcher, L. ; Pavan, P. ; Taylor, W. ; Kirsch, P.D.

  • fYear
    2010
  • fDate
    16-19 May 2010
  • Firstpage
    1
  • Lastpage
    2
  • Abstract
    In TANOS stuctures in retention, the major decrease in the programmed threshold voltage is found to be caused by the Vt sensing (IdVg measurements) rather than by intrinsic charge loss (when no bias is applied). This Vt decrease can be understood within the process of the temperature-activated charge transport through the Al2O3 blocking oxide. The charge loss can be minimized when Vt sensing time is decreased down to micro seconds. Blocking oxides engineered by adding a thin SiO2 layer at the SiN/AlO interface demonstrate significant suppression of the charge loss.
  • Keywords
    CMOS memory circuits; aluminium compounds; circuit simulation; interface states; silicon compounds; tantalum compounds; TANOS devices; TANOS stuctures; TaN-Al2O3-Si3N4-SiO2; Vt sensing measurements; intrinsic charge loss; programmed threshold voltage; temperature-activated charge transport; Aluminum oxide; Charge measurement; Current measurement; Electrodes; Electron traps; Loss measurement; Process control; Silicon compounds; Time measurement; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Memory Workshop (IMW), 2010 IEEE International
  • Conference_Location
    Seoul
  • Print_ISBN
    978-1-4244-6719-8
  • Electronic_ISBN
    978-1-4244-7668-8
  • Type

    conf

  • DOI
    10.1109/IMW.2010.5488409
  • Filename
    5488409