Indium gallium arsenide on silicon interband tunnel diodes for NDR-based memory and steep subthreshold slope transistor applications

Advances in materials growth techniques are enabling new device concepts, circuit approaches, and system architectures to enhance and extend CMOS technology such as tunneling-based static random access memory and steep subthreshold slope III-V tunneling field effect transistors (TFETs). TFETs are essentially gated Esaki (or backward) diodes operating in the reverse (Zener) direction. Recently, the authors reported on record III-V tunnel diodes fabricated on Si via a technique known as aspect ratio trapping (ART). To the knowledge of the authors, the high PVCR (56) was the fourth highest reported for any tunnel diode structure on any substrate. In this study, the authors report on (i) the temperature dependence of these devices, (ii) the insensitivity of tunnel current (forward and Zener) to temperature, and (iii) the absence of mid-gap states in the excess current.