A Method to Prevent Strong Snapback in LDNMOS for ESD Protection

Author

Hang Fan ; Lingli Jiang ; Bo Zhang

Author_Institution

Sch. of Microelectron. & Solid-States Electron., Univ. of Electron. Sci. & Technol. of China, Chengdu, China

Volume

13

Issue

1

fYear

2013

fDate

Mar-13

Firstpage

50

Lastpage

53

Abstract

High injection electron current in an LDNMOS can lead to a strong snapback and latch-up-like characteristic. It is susceptible to latch-up-like in high-voltage ICs, if its holding voltage is lower than the power supply voltage. A method to raise the LDNMOS holding voltage is proposed and verified in a 0.35-μm 20-V/5-V BCD process without additional masks. It is realized by adding a relative high doping Nw provided for a 5-V PMOS in the drain region. The doping concentration in the Nw is higher than the injection electron density from the source under ESD stress. The Nw can extend the length of the space-charge region and lead to a higher voltage drop and high strong snapback current. This way, we get an LDNMOS with holding voltage higher than 24 V.

Keywords

BIMOS integrated circuits; doping profiles; electrostatic discharge; space charge; BCD process; ESD protection; LDNMOS holding voltage; PMOS; doping concentration; drain region; high injection electron current; high-voltage integrated circuit; latch-up-like characteristic; size 0.35 mum; space-charge region; strong snapback current; strong snapback prevention; voltage 20 V; voltage 5 V; voltage drop; Doping; Electric fields; Electrostatic discharges; Robustness; Space charge; Stress; Transistors; ESD; LDNMOS; high holding voltage;

fLanguage

English

Journal_Title

Device and Materials Reliability, IEEE Transactions on

Publisher

ieee

ISSN

1530-4388

Type

jour

DOI

10.1109/TDMR.2012.2210043

Filename

6248198