• DocumentCode
    2693691
  • Title

    Design, fabrication and evaluation of a 5-inch wafer scale neural network LSI composed on 576 digital neurons

  • Author

    Yasunaga, Moritoshi ; Masuda, Noboru ; Yagyu, Masayoshi ; Asai, Mitsuo ; Yamada, Minoru ; Masaki, Akira

  • fYear
    1990
  • fDate
    17-21 June 1990
  • Firstpage
    527
  • Abstract
    A wafer-scale-integration (WSI) neural network has been fabricated and evaluated. 576 digital neurons are integrated and interconnected with each other on a 5-in silicon wafer by using 0.8-μm CMOS. Neural functions are faithfully mapped to binary digital circuits. The 9-bit output and the 8-bit synapse weight of each neuron are variable. A time-sharing digital bus architecture overcomes the disadvantage of digital neuron circuits. This WSI neural network can be connected with a host computer and used for a wide range of artificial neural networks. The 16-city traveling salesman problem could be solved in less than 0.1 s by using this network. This speed was 10 times faster than a Hitachi supercomputer. Larger artificial neural networks can be realized by simply connecting WSIs
  • Keywords
    CMOS integrated circuits; VLSI; digital integrated circuits; neural nets; 0.8-μm CMOS; 16-city traveling salesman problem; 5-inch wafer scale neural network; 576 digital neurons; 8-bit synapse weight; 9-bit output; Hitachi neural net chip; WSI neural network; time-sharing digital bus architecture;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Neural Networks, 1990., 1990 IJCNN International Joint Conference on
  • Conference_Location
    San Diego, CA, USA
  • Type

    conf

  • DOI
    10.1109/IJCNN.1990.137618
  • Filename
    5726578