Title :
High temperature operation of ISE devices and circuits
Author :
Vu, D.P. ; Boden, M.J. ; Henderson, W.R. ; Cheong, N.K. ; Zavracky, P.M. ; Adams, D.A. ; Austin, M.M.
Author_Institution :
Kopin Corp., Taunton, MA, USA
Abstract :
Summary form only given. The high-temperature behavior of devices and circuits fabricated in ISE (isolated silicon epitaxy) SOI wafers and in bulk Si wafers is discussed. The advantages of SOI over bulk circuits under high-temperature operation result from reduced leakage current due to the absence of well junction in CMOS and the reduction of source and drain to body junction areas. One to two orders of magnitude reduction of leakage current for ISE devices compared to equivalent bulk devices is observed at 300°C. At this temperature, junction leakage in bulk devices reaches several tens of microamps. These results indicate the leakage at high temperature is dominated by the diffusion of carriers through junctions (proportional to ni2(T)). Another confirmation of this observation is provided by the recovery time of drain-source transient of a depletion-mode MOSFET as a function of temperature when a step bias is applied to the gate
Keywords :
CMOS integrated circuits; insulated gate field effect transistors; integrated memory circuits; leakage currents; random-access storage; semiconductor epitaxial layers; semiconductor technology; semiconductor-insulator boundaries; 300 C; CMOS; ISE devices; SOI wafers; SRAM; Si wafers; Si-SiO2; carrier diffusion; depletion-mode MOSFET; drain-source transient; high-temperature operation; isolated silicon epitaxy; junction leakage; leakage current; recovery time; semiconductor; well junction; Circuits; Content addressable storage; Dielectrics; Epitaxial growth; Isolation technology; Leakage current; Metallization; Process control; Proportional control; Temperature;
Conference_Titel :
SOS/SOI Technology Conference, 1989., 1989 IEEE
Conference_Location :
Stateline, NV
DOI :
10.1109/SOI.1989.69815