A CCD based neural network integrated circuit with 64K analog programmable synapses

A report is presented on the design, fabrication, and testing of a neural network integrated circuit with 65536 analog programmable synapses (256 fully interconnected neurons). The integrated circuit utilizes charge-coupled devices (CCDs) based on a generic architecture that the authors proposed (1987). Preliminary testing of the CCD neural processor indicates that the operating speed is 0.5×10⁹ analog interconnect updates/s. Loading of the synaptic interaction matrix can be accomplished either electrically or optically within 0.5 ms or 1 ms, respectively