A time-multiplexed FPGA

Author

Trimberger, Steve ; Carberry, Dean ; Johnson, Anders ; Wong, Jennifer

Author_Institution

Xilinx Inc., San Jose, CA, USA

fYear

1997

fDate

16-18 Apr 1997

Firstpage

22

Lastpage

28

Abstract

This paper describes the architecture of a time-multiplexed FPGA. Eight configurations of the FPGA are stored in on-chip memory. This inactive on-chip memory is distributed around the chip, and accessible so that the entire configuration of the FPGA can be changed in a single cycle of the memory. The entire configuration of the FPGA can be loaded from this on-chip memory in 30 ns. Inactive memory is accessible as block RAM for applications. The FPGA is based on the Xilinx XC4000E FPGA, and includes extensions for dealing with state saving and forwarding and for increased routing demand due to time-multiplexing the hardware

Keywords

SRAM chips; field programmable gate arrays; network routing; reconfigurable architectures; time division multiplexing; FPGA architecture; SRAM; Xilinx XC4000E FPGA; block RAM; configurations; field programmable gate array; inactive memory; on-chip memory; reconfigurable architecture; routing demand; state forwarding; state saving; time-multiplexed FPGA; Engines; Field programmable gate arrays; Hardware; Logic arrays; Logic design; Logic devices; Random access memory; Read-write memory; Reconfigurable logic; Routing;

fLanguage

English

Publisher

ieee

Conference_Titel

Field-Programmable Custom Computing Machines, 1997. Proceedings., The 5th Annual IEEE Symposium on

Conference_Location

Napa Valley, CA

Print_ISBN

0-8186-8159-4

Type

conf

DOI

10.1109/FPGA.1997.624601

Filename

624601