• DocumentCode
    2694654
  • Title

    Fitness inheritance in evolutionary and multi-objective high-level synthesis

  • Author

    Pilato, Christian ; Palermo, Gianluca ; Tumeo, Antonino ; Ferrandi, Fabrizio ; Sciuto, Donatella ; Lanzi, Pier Luca

  • Author_Institution
    Dipt. di Elettronica e Informazione, Milano
  • fYear
    2007
  • fDate
    25-28 Sept. 2007
  • Firstpage
    3459
  • Lastpage
    3466
  • Abstract
    The high-level synthesis process allows the automatic design and implementation of digital circuits starting from a behavioral description. Evolutionary algorithms are very widely adopted to approach this problem or just part of it. Neverthless, some concerns regarding execution times exist. In evolutionary high-level synthesis, design solutions have to be evaluated to extract information about some figures of merit (such as performance, area, etc.) and to allow the genetic algorithm to evolve and converge to Pareto-optimal solutions. Since the execution time of such evaluations increases with the complexity of the specification, the overall methodology could lead to unacceptable execution time. This paper presents a model to exploit fitness inheritance in a multi-objective optimization algorithm (i.e. NSGA-II) by substituting the expensive real evaluations with estimations based on closeness in an hypothetical design space. The estimations are based on the measure of the distance between individuals and a weighted average of the fitnesses of the closest ones. The results shows that the Pareto-optimal set obtained by applying the proposed model well approximates the set obtained without fitness inheritance. Moreover, the overall execution time is reduced up to the 25% in average.
  • Keywords
    Pareto optimisation; genetic algorithms; high level synthesis; Pareto-optimal solutions; digital circuits; evolutionary algorithms; evolutionary high-level synthesis; fitness inheritance; genetic algorithm; multiobjective optimization algorithm; Algorithm design and analysis; Data mining; Digital circuits; Evolutionary computation; Field programmable gate arrays; Genetic algorithms; Hardware design languages; High level synthesis; Integrated circuit interconnections; Resource management;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Evolutionary Computation, 2007. CEC 2007. IEEE Congress on
  • Conference_Location
    Singapore
  • Print_ISBN
    978-1-4244-1339-3
  • Electronic_ISBN
    978-1-4244-1340-9
  • Type

    conf

  • DOI
    10.1109/CEC.2007.4424920
  • Filename
    4424920