Title :
The swappable logic unit: a paradigm for virtual hardware
Author_Institution :
Dept. of Comput. Sci., Edinburgh Univ., UK
Abstract :
Swappable Logic Units (SLUs) were introduced by the author previously (1996) to play a role in virtual hardware subsystems that is analogous to the role of pages or segments in virtual memory subsystems. The intention is that a conventional operating system can be extended to manage SLU circuitry implemented using FPGA real estate. In order to minimise operating system overheads, two particular SLU-based virtual hardware models were deemed practical: a “sea of accelerators” model and a “parallel harness” model. This paper looks in some detail at how SLUs will fit within the overall environment of a fairly conventional hardware/software system. First, there is a discussion of the FPGA-based hardware environment for SLUs, followed by a discussion of the software environment from which SLUs might be used. After this, there is a description of the operational properties that SLUs can have, and how these fit in with the two virtual hardware models. Finally, proposals for standard interfaces between SLUs and their environment are discussed. These interfaces can be regarded as constraints on the designers of SLU circuitry or, more positively, as suppliers of an enriched context within which such circuitry operates. The overall impact of the work presented in the paper is to show that it is feasible to incorporate configurable hardware within traditional computer systems that use high-level language programs and computer operating systems. That is, it should not always be necessary to devise special-purpose hardware/software systems to realise custom computing
Keywords :
field programmable gate arrays; logic design; virtual machines; configurable hardware; high-level language programs; operating system overheads; parallel harness; sea of accelerators; swappable logic unit; virtual hardware; virtual memory subsystems; Acceleration; Circuits; Computer science; Field programmable gate arrays; Hardware; Logic; Operating systems; Power system modeling; Registers; Software systems;
Conference_Titel :
Field-Programmable Custom Computing Machines, 1997. Proceedings., The 5th Annual IEEE Symposium on
Conference_Location :
Napa Valley, CA
Print_ISBN :
0-8186-8159-4
DOI :
10.1109/FPGA.1997.624607