DocumentCode
2695360
Title
Systolic array implementations of neural nets on the MasPar MP-1 massively parallel processor
Author
Chinn, G. ; Grajski, K.A. ; Chen, C. ; Kuszmaul, C. ; Tomboulian, S.
fYear
1990
fDate
17-21 June 1990
Firstpage
169
Abstract
It is shown that systolic array design techniques commonly used by VLSI designers can be used to realize neural nets on parallel single-instruction-multiple-data (SIMD) machines. The MasPar MP-1 is well suited for implementation of 2D systolic arrays because of its X-network communications. Implementation of neural networks can be further optimized by taking advantage of other architectural features: indirect addressing, register-based CPU, and large addressable local memories. An application to speech recognition is discussed
Keywords
neural nets; parallel architectures; parallel machines; speech recognition; systolic arrays; 2D systolic arrays; MasPar MP-1; VLSI designers; X-network communications; architectural features; indirect addressing; large addressable local memories; massively parallel processor; neural nets; parallel single-instruction-multiple-data; register-based CPU; speech recognition; systolic array design techniques;
fLanguage
English
Publisher
ieee
Conference_Titel
Neural Networks, 1990., 1990 IJCNN International Joint Conference on
Conference_Location
San Diego, CA, USA
Type
conf
DOI
10.1109/IJCNN.1990.137711
Filename
5726670
Link To Document