Title :
Design and analysis of a CMOS SOS/SOI receiver for a radiation hard computer
Author :
Walker, W. ; Martinez, M. ; Lane, H. ; Worley, E.
Author_Institution :
Rockwell Int. Corp., Newport Beach, CA, USA
Abstract :
Summary form only given. The design of a clock receiver with a high-capacitance output drive that required special layout considerations to obtain a high-speed input protection network is discussed. The receiver layout used a crossing poly pattern to reduce thermal hot spots and improve reliability. Also, the design ground rules for pulse current loading on the small-cross-section clock interconnect metallization lines were related to the DC current rating. Finally, by applying a weak forward bias to the body of the NFET of a ratioed CMOS inverter, it was possible to realize a more ideal TTL buffer with respect to switch point and temperature characteristics
Keywords :
CMOS integrated circuits; clocks; integrated logic circuits; logic design; radiation hardening (electronics); receivers; transistor-transistor logic; CMOS SOS/SOI receiver; DC current rating; NFET; Si on insulator; Si on sapphire; Si-Al2O3; TTL buffer; clock interconnect metallization lines; clock receiver; crossing poly pattern; design ground rules; high-capacitance output drive; high-speed input protection network; pulse current loading; radiation hard computer; ratioed CMOS inverter; receiver layout; reliability; temperature characteristics; thermal hot spots; Capacitance; Clocks; Conductivity; Drives; Power supplies; Protection; Switches; Temperature dependence; Temperature sensors; Threshold voltage;
Conference_Titel :
SOS/SOI Technology Conference, 1989., 1989 IEEE
Conference_Location :
Stateline, NV
DOI :
10.1109/SOI.1989.69816
