A 64b 4-issue out-of-order execution RISC processor

Author

Shen, G. ; Patkar, N. ; Ando, H. ; Chang, D. ; Chen, C. ; Chien Chen ; Chen, F. ; Forssell, P. ; Gmuender, J. ; Kitahara, T. ; Hungwen Li ; Lyon, D. ; Montoye, R. ; Peng, L. ; Savkar, S. ; Sherred, J. ; Simone, M. ; Swami, R. ; Tovey, D. ; Williams, T.

Author_Institution

HaL Computer Systems, Campbell, CA, USA

fYear

1995

fDate

15-17 Feb. 1995

Firstpage

170

Lastpage

171

Abstract

This processor is the first implementation of the SPARC V9 64b instruction set architecture and has an estimated performance exceeding 256 SPECint92 and 330 SPECfp92 at 154 MHz. The R1 processor consists of one CPU chip, one memory management unit (MMU), four cache chips, and one clock chip mounted on a ceramic multi-chip module (MCM). The processor utilizes superscalar instruction issue, register renaming, and data flow execution to exploit instruction-level parallelism.

Keywords

data flow computing; instruction sets; microprocessor chips; parallel architectures; reduced instruction set computing; 154 MHz; 4-issue out-of-order execution; 64 bit; CPU chip; R1 processor; RISC processor; SPARC V9 64b instruction set architecture; cache chips; ceramic multi-chip module; clock chip; data flow; instruction-level parallelism; memory management unit; register renaming; superscalar instruction issue; Ceramics; Clocks; Computer aided instruction; Computer architecture; Memory management; Out of order; Packaging; Parallel processing; Reduced instruction set computing; Registers;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1995. Digest of Technical Papers. 41st ISSCC, 1995 IEEE International

Conference_Location

San Francisco, CA, USA

ISSN

0193-6530

Print_ISBN

0-7803-2495-1

Type

conf

DOI

10.1109/ISSCC.1995.535508

Filename

535508