Title :
Signal delay in RC networks with floating capacitors
Author_Institution :
Comput. Eng. Board of Studies, California Univ., Santa Cruz, CA, USA
Abstract :
A scheme is presented for the estimation of signal delay in RC networks with floating capacitors. The scheme involves finding signal delays in the network with the floating capacitors either replaced by open circuits or short circuits. Preliminary experiments have shown that the scheme is viable and could be used to build an efficient RC simulator that handles RC networks with floating capacitors. The results are pertinent to the use of linear lumped RC networks in timing simulators to model MOS digital circuits
Keywords :
delays; linear network analysis; lumped parameter networks; MOS digital circuit modelling; RC networks; capacitive coupling; floating capacitors; linear lumped networks; open circuits; short circuits; signal delay; timing simulators; Circuit simulation; Computational modeling; Delay effects; Delay estimation; Digital circuits; Intelligent networks; MOS capacitors; Parasitic capacitance; Timing; Wires;
Conference_Titel :
Circuits and Systems, 1988., IEEE International Symposium on
Conference_Location :
Espoo
DOI :
10.1109/ISCAS.1988.15528
