DocumentCode :
2696257
Title :
The RAW benchmark suite: computation structures for general purpose computing
Author :
Babb, Jonathan ; Frank, Matthew ; Lee, Victor ; Waingold, Elliot ; Barua, Rajeev ; Taylor, Michael ; Kim, Jang ; Devabhaktuni, Srikrishna ; Agarwal, Anant
Author_Institution :
Lab. for Comput. Sci., MIT, Cambridge, MA, USA
fYear :
1997
fDate :
16-18 Apr 1997
Firstpage :
134
Lastpage :
143
Abstract :
The RAW benchmark suite consists of twelve programs designed to facilitate comparing, validating, and improving reconfigurable computing systems. These benchmarks run the gamut of algorithms found in general purpose computing, including sorting, matrix operations, and graph algorithms. The suite includes an architecture-independent compilation framework, Raw Computation Structures (RawCS), to express each algorithm´s dependencies and to support automatic synthesis, partitioning, and mapping to a reconfigurable computer. Within this framework, each benchmark is portably designed in both C and Behavioral Verilog and scalably parameterized to consume a range of hardware resource capacities. To establish initial benchmark ratings, we have targeted a commercial logic emulation system based on virtual wires technology to automatically generate designs up to millions of gates (14 to 379 FPGAs). Because the virtual wires techniques abstract away machine-level details like FPGA capacity and interconnect, our hardware target for this system is an abstract reconfigurable logic fabric with memory-mapped host I/O. We report initial speeds in the range of 2X to 1800X faster than a 2.82 SPECint95 SparcStation 20 and encourage others in the field to run these benchmarks on other systems to provide a standard comparison
Keywords :
field programmable gate arrays; logic CAD; performance evaluation; reconfigurable architectures; sorting; Behavioral Verilog; C language; FPGA capacity; RAW benchmark suite; SPECint95 SparcStation 20; architecture-independent compilation framework; automatic synthesis; computation structures; general purpose computing; graph algorithms; logic emulation system; mapping; matrix operations; partitioning; reconfigurable computing systems; sorting; virtual wires; Automatic logic units; Emulation; Fabrics; Field programmable gate arrays; Hardware design languages; Logic design; Partitioning algorithms; Reconfigurable logic; Sorting; Wires;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Field-Programmable Custom Computing Machines, 1997. Proceedings., The 5th Annual IEEE Symposium on
Conference_Location :
Napa Valley, CA
Print_ISBN :
0-8186-8159-4
Type :
conf
DOI :
10.1109/FPGA.1997.624613
Filename :
624613
Link To Document :
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